1. Field of the Invention
The present invention relates to the packaging of semiconductor chips and, more particularly, to packaging of optoelectronic chips on a wafer scale before the wafer is diced into chips. Particular emphasis is placed on integrating arrays of micro-optical elements to arrays of vertical-cavity surface-emitting lasers.
2. Description of the Prior Art
Fabrication of electronic circuits and optoelectronic devices has advanced to a state where the majority of the cost of semiconductor components lies not in the semiconductor processing, but in the packaging of the components. For electronics components, packaging typically involves electrical connection of the microscopic circuitry to macroscopic elements, e.g., pins, heatsinking, and protection from environmental hazards such as dust. Packaging of optoelectronic components such as lasers additionally involves optical elements to manipulate light emitted from or entering into the optoelectronic devices. The major reason for the high cost of semiconductor packaging relative to semiconductor processing is that the packaging is performed on a chip-by-chip basis, i.e., one component at a time. By contrast, semiconductor processing takes place on a wafer scale, a single wafer typically containing hundreds of chips. Performance of any part of the semiconductor packaging process on a wafer scale, rather than a chip scale, will greatly decrease cost and increase manufacturing throughput.
Wafer scale packaging generally involves the integration of dissimilar materials. A necessary condition is that integration of one component with another does not interfere with the operation of, or subsequent packaging of, either component. For example, with light-emitting optoelectronic devices, such as vertical-cavity surface-emitting lasers (VCSELs), integrated lenses must comprise an optically transparent material and the lenses must not prevent electrical contacting. Conventional edge-emitting semiconductor lasers are not suitable for wafer scale packaging because light propagates parallel to the wafer surface and the wafer must be cleaved, sawn or etched to complete the laser structure to allow for the propagation of this light. VCSELs emit radiation in a direction perpendicular to the wafer surface. In contrast to the elliptical and astigmatic beam quality of edge emitting lasers, VCSELs advantageously emit circularly symmetric, low divergence Gaussian beams which may be collected by lenses of simple construction. VCSELs, moreover, may be readily made into two-dimensional laser arrays as well as fabricated in extremely small sizes. Accordingly, two-dimensional VCSEL arrays have various applications in the fields of optical memory, laser printing and scanning, optical communications, optoelectronic integrated circuits, optical computing, optical interconnection, etc.
For the purposes of this application, packaging is defined as "the integration of components either comprising dissimilar materials or having separate fabrication processes on different wafers, each component undergoing fabrication processes either before, during or after the integration takes place." A package is a component which results from packaging. An example of the monolithic integration of VCSELs with transistors is disclosed by Olbright and Jewell, in U.S Pat. No. 5,283,447. Since the VCSELs and transistors comprise similar materials and are fabricated on the same wafer, the procedure is not considered to be packaging; rather, it is the fabrication of an opto-electronic integrated circuit, or OEIC.
Shifrin and Hunsperger, in U.S. Pat. No. 4,677,740, describe an opto-isolator in which Light-Emitting Diodes (LEDs) are monolithically integrated with detectors. The Shifrin and Hunsperger process also is an OEIC fabrication. In a similar manner, Ehrfeld et al., in U.S. Pat. No. 5,194,402, describes the fabrication of sensor structures on top of electronic circuits, the sensor fabrication being an extension of the electronic circuit fabrication process. Kolbas, in U.S. Pat. No. 4,532,694, describes a method by which etching and subsequent semiconductor growth and polishing on a wafer produces a material structure on which electronic and optoelectronic devices may be subsequently fabricated. The Kolbas method relates to material preparation rather than packaging.
Optoelectronic packaging often involves the integration of optoelectronic elements, such as lasers or photodetectors, with optical elements such as lenses. Slawek et al., in U.S. Pat. No. 3,704,375, describes a process in which dielectric materials are deposited onto detector elements prior to dicing the wafer into chips.
Other patents relating to packaging of LEDs and photodetectors include, for example, Spaeth et al., U.S. Pat. No. 4,875,750, which describes the etching of holes into a carrier chip substrate and subsequent placement of a spherical lens within the substrate. When the carder chip is integrated to the LED chip, the lens directs the light emitted from the LED. Integrated packaging on a scale beyond the chip level is not disclosed or suggested.
Packaging on a scale greater than one element at a time is very limited in the prior art and it is usually performed on the side of the wafer opposite to the side on which the LEDs are fabricated. An example of this type of packageing is taught by Cina et al., in U.S. Pat. No. 5,042,709. Cina et al. describe a process for packaging arrays of lasers and arrays of fibers which requires mounting both lasers and fibers to a third substrate. The Cina et al. process is not applicable for two-dimensional, i.e., full wafer scale, packaging. The Cina et al. process also requires a complicated dicing procedure.
Haitz, in U.S. Pat. No. 5,087,949, describes the sawing of grooves on the back side of an LED wafer to create multiple planar refracting surfaces which directs light, emitted through the substrate, in a preferred direction. Buckley and Ostermayer, in U.S. Pat. No. 4,391,683, describe the use of photoetching for the formation of lenses on the back sides of LED wafers to enhance coupling of the light into optical fibers. In both Haltz and Buckley, optical elements are formed into the LED substrate material on the back side of the substrate. No integration of dissimilar materials or separate fabrication processes is disclosed and therefore, the process is not a packaging process.
Heinen, in U.S. Pat. Nos. 4,740,259 and 4,841,344, describes the adhesive mounting of spherical lenses onto mesas etched on the back side of an LED wafer. Separation into individual LEDs is performed after the lenses are mounted. In Heinen's apparatus, the spherical lenses are fabricated separately before mounting on a vacuum holding apparatus. There is no described means for mounting the spherical lenses on the holding apparatus, nor is it at all obvious to one skilled in the art as to whether large numbers of lenses may be mounted simultaneously.
Jokerst et al., in U.S. Pat. No. 5,244,818, describe a liftoff process in which separately fabricated devices may be integrated by lifting devices off one substrate and bonding them to another. Jokerst et al. neither disclose nor suggest dicing the resultant hybrid structure into chips after the integration. Furthermore, it is not clear whether the Jokerst et al. process is extensible to wafer-scale integration, mainly due to the difficulties encountered for maintaining precise alignment over large wafer areas, especially if the wafers have different coefficients of thermal expansion.
Liftoff is also described by Fossum et al., in U.S. Pat. No. 5,236,871; however, Fossum et al. does not describe or suggest wafer-level integration or any means for achieving such integration.
The prior art relating to the integrated packaging of optoelectronic components is found to be severely restricted. In many cases, the packaging is performed on the back side of the wafer, necessitating that the wafer material be transparent to the wavelength of the emitted light, thereby restricting the materials/wavelengths combinations for which the techniques are applicable. Furthermore, since electrical contacting on the back side of the wafer is minimal, no techniques are disclosed or suggested for maintaining or improving the ability to electrically contact the wafer after the optical elements are integrated. In no circumstance are components having substantially planar surfaces integrated to optoelectronic or electronic wafers on a wafer scale with full generality of top side and back side integration.